Phase-locked loops (PLLs) operate primarily as clock frequency multipliers, and the output clock is generated by multiplying an input clock frequency by an integer divider value, “N”. Fractional-N values can be used as well.
A common prior art implementation of fractional N values is to dynamically adjust the integer value of N so that the time-average value of N contains both an integer and a fractional component. However, the dynamic adjustment causes instantaneous phase errors within the PLL that must be constantly corrected. These phase errors result in what is commonly referred to as “fractional-N spurs,” which are undesired spectral degradation of the PLL output clock. Delta-sigma modulation (DSM) techniques are used to suppress the magnitude of fractional-N spurs embedded in the clock, but there is a limit to the extent this impurity can be filtered out.
PRIOR ART FIG. 1A is a block diagram of a traditional PLL 100A. Upon startup of the PLL 100A, the voltage-controlled ring oscillator (VCO) 140 produces a clock in K phases that exhibits an arbitrary “free-running” frequency of value FVCO. One of the K phases of the clock is given to the integer-based divide-by-N unit 150, and a clock with frequency FVCO/N, with N=NDIV_INT being a positive integer is generated. The divide-by-N clock exhibits a pulse with logical value 1 of width TVCO, where TVCO=1/FVCO. The remainder of the clock cycle is logical 0, with duration (N−1)×TVCO. This divided clock is labeled as the feedback clock.
The phase detector 110 will compare the phase difference between the reference clock and the feedback clock, and generate an error pulse of width equal to the phase difference. The phase difference is converted to electrical current by the charge pump 120, and the current is terminated in the loop filter 130 to produce an updated control voltage to the VCO 140.
On every cycle of the reference clock, the phase detector will generate a new error pulse that is processed by the charge pump and loop filter to update the voltage that controls the VCO 140. As (1) the frequency of the VCO clock approaches N×Fref, with Fref being the frequency of the reference clock, and (2) the phase difference between the reference clock and the feedback clock approaches zero, the width of the error pulse produced by the phase detector will approach zero.
A PLL 100A that is in the process of achieving frequency and phase lock is considered to be in a state of “acquisition.” If the phase detector 110 produces a “negligible” error pulse, the PLL 100A is considered to have completed acquisition, and is in a state of “tracking” During the tracking state, the PLL 100A continues to refresh the error signal (even if it is zero value), so that the PLL 100A corrects minor deviations of phase and frequency from its lock point every update cycle of the reference clock.
A PLL 100A whose divide-by-N value remains static during operation is termed an “integer-N PLL.” A PLL 100A whose divide-by-N value is dynamically adjusted every cycle of the feedback clock will exhibit an effective divide-by-N value, Neff, whose time-average value consists of an integer and a fractional component. Such a PLL is termed a “fractional-N PLL.” For example, if the divided-by-N value alternates between values N and N+1 for every cycle of the feedback clock, the time average value of Neff will be N+½.
A general fractional-N PLL can exhibit dynamic divide values ranging from N−L to N+L, with L being a positive integer such that L<N. For example, if L=3, the possible dynamic values of the divide-by-N unit are N+{−3,−2,−1,0,+1,+2,+3}. Irrespective of the value of L, the divide-by-N value will be adjusted every cycle of the feedback clock by a integer value. Each time the value is updated, the phase difference at the input of the phase detector will have a minimum value of TVCO, which means the width of the error pulse will also be a minimum of TVCO.
The constant generation of new phase error every cycle of the feedback clock introduces “spurs” into the spectral content of the VCO clock.
Random scrambling (with normal statistical distribution) of the divide-by-N value, with a time-average bias at Neff, causes the phase error to be a phase-domain “white” noise process over time. In the frequency domain, the energy of a white noise process is uniformly distributed over all frequencies.
From the standpoint of either the reference clock or feedback clock, the frequency response of the PLL to the VCO clock appears as a phase-domain low-pass filter. If the divide-by-N value is randomly scrambled, the high-frequency power of the error signal will be attenuated while the low-frequency power is preserved. Consequently, the spur energy of the fractional-N PLL is caused by the preservation of this low-frequency power.
In lieu of random scrambling, a delta-sigma modulator (DSM) 160 is most often employed to scramble the divide-by-N value, while preserving the time-average bias at Neff. A DSM is a non-linear digital filter that partially removes low-frequency energy and relocates it to higher frequencies. The total energy across frequencies remains the same, but the distribution of power is weighted towards high frequencies. Use of a DSM 160 for fractional-N synthesis lowers overall spur energy by reducing in-band error signal energy at the output of the phase detector.
PRIOR ART FIG. 1B is a block diagram of an alternative PLL 100B implementation that seeks to reduce the spur energy of PLL 100A by employing a multi-phase, multi-modulus divider instead of the single-phase divider of PLL 100A. The plurality of VCO phases are used to sample the divider output with flip-flop circuits, resulting in a plurality of divided clock phases with phase spacings identical to the plurality of VCO phases.
A combination of prescaler divider (divide by P/P+1) 170, divide-by-M counter 173, and divide-by-A counter 175 constitute the multi-modulus divider, with a combined divide value of (P×M+A). The plurality of divided clock phases, each with period TVCO×(P×M+A), is presented to the input of a clock selection unit (MUX) 177, and the output of the MUX 177 is arranged as the feedback branch of the PLL 100B that connects to the input of the phase detector 180.
A controller 182 provides dynamic values of P, M, and A, as well as a phase control value that selects one of the plurality of divided clock phases to be passed through to the output of the clock selection unit 177. The controller 182 produces such signals such that a desired “clock-wise” rotation of phase selection through the MUX 177 is sustained and produces a fractional component to the total multi-modulus divide value. The controller 182 will also produce a dynamic change in prescaler value to ensure the fractional component does not disappear when the final phase of divided clock is replaced by the first phase of divided clock at the output of the clock selection unit 177. A generic modulator is claimed to enhance fractional resolution by scrambling the input of the controller over time.
While the general strategy of multi-phase clock division is sound, PLL 100B restricts the divider implementation to an arrangement of a pre-scaler and two counters, M and A. This arrangement is specific for PLLs used in some types of wireless radio applications, but does not satisfy implementation for a general class of PLLs with a simple counter divider implementation, whose divide value is a simple integer value N, rather than (P×M+A).
Further, the arrangement of the prior-art retimer circuit 184 has the divided clock sampled (retimed) by the rising edge of the clock that produces the divided clock. This arrangement is prone to produce setup violations in the sampling operation, so a more robust retimer that retains plenty of setup and hold time margins is desirable. Also, PLL 100B implements a fractional generation controller 182 that only allows for positive fractional divider values, implemented by rotating the selection of the plurality of divided clock phases through the clock selection unit (MUX) in a clock-wise sequence. This is problematic for generation of very low-value fractional divide values close to zero. Moreover, the implementation of the multi-modulus divider (including the combination of prescaler divider [divide by P/P+1] 170, divide-by-M counter 173, and divide-by-A counter 175) of PLL 100B requires a range extension control to preserve uniform fractional divide value resolution over a large range.